As a member of the digital backend team, the candidate will be responsible for the physical implement(from netlist to GDSII) , physical verification, and other back-end activities.
1. Responsible for block level physical design from netlist to GDSII including floorplan, place,CTS and route, power analysis, crosstalk analysis, timing closure and physical verification.
2.Responsible for static timing analysis anr rc extraction.
3.Responsible for physical verification,including DRC,LVS and ERC.
4. Also responsible for full chip implementation.
5. Be familiar with eco flow.
6.Work with front-end densigners to optimize performance/power/area.
1. More than one year of PR related work experience.
2.Familiar with physical design flow/tools(Encounter/Innovus/ICC/QRC/Tempus and so on).Experience with Cadence Innovus is a plus.
3. Successful tapeout experience is a strong plus.
4. Good programming skill(Perl/TCL) is a plus.
5.Good problem solving and debugging skills.
6. Must be a good team player and have a good communication skills.