Receiving Email: Sohee Moon <firstname.lastname@example.org>; Jewel Huang email@example.com ( Jewel may help screen resume only with Mandarin)
Job Description and Requirements
Responsibilities include EDA software product application & deployment, design methodology development, design implementation RTL2GDS and winning competitive benchmark, test chip design for advanced process node. Position requires working closely with R&D, product CAE & marketing inside business unit while interfacing with field application consultants & customer outside BU. Must be able to work independently with minimum supervision to complete assignment.
BSEE minimum, MSEE preferred with 5+ years of direct hands-on design experience in using backend physical digital design Place & Route required.
Must be expert of IC Compiler II. Design Compiler, PrimeTime & ECO experience a plus. Must have good scripting skills. Strong understanding of ASIC design flow,
high performance ARM processor design flow desired and hierarchical design methodologies. Self-motivated & independently work alone with strong communication skill, good command of English language plus people skill required.
Synopsys,Inc.Nasdaq:SNPS,headquartered in Mountain View,California,creates leading electronic design automation(EDA)tools for the global electronics market.The company delivers advanced design technologies and solutions to developers of complex integrated circuits,electronic systems and systems on a chip.Synopsys also provides consulting and support services to simplify the overall IC design process and accelerate time to market for its customers.
Over the past several years,Synopsys has entered into partnerships with IBM,SGS-Thomson,SEMATEC,Toshiba and others to develop tools and design flows for complex IC and ASIC designs at 0.25 micron and below.The Company has also partnered with programmable logic vendors and other EDA companies to tackle issues ranging from the impact of complex silicon in programmable devices to sound design reuse strategies.
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