Be a part of the Central Engineering IP team at Marvell china. Main responsibility is perform analog layout and related drc/lvs/erc/ant verification, debugging and violations fix. Will be responsible for all levels of analog layout from block level up to the IP/AFE most top level integration and physical verification. You will communicate and get directions from experienced analog design engineers and analog layout engineers to guarantee high quality.
- BS degree, major in electronic engineering, computer science, or equivalent.
- Good communication skills in written and spoken English.
- Good team work and communication skills. Hardworking and self-motivated under a high competition design/layout team.
- Understanding basic characteristic of transistor, resistor, capacitor and diode.
- Understanding of layout impact on device matching, noise coupling from signal, supply and substrate. Understanding the importance of signal flow, power/ground structure and block placement in layout floorplan.
- Experience with unix/linux, cadence virtuoso, synopsys laker is plus.
- Experience with calibre drc/lvs is plus.
We believe that infrastructure powers progress. That execution is as essential as innovation. That better collaboration builds better technology. At Marvell, We go all in with you. Focused and determined, we unite behind your goals as our own. We leverage our unrivaled portfolio of infrastructure technology to identify the best solution for your unique needs. And we sit shoulder-to-shoulder with your teams to build it. Agile in our thinking, and our partnerships, we look for unexpected connections that deliver a competitive edge and reveal new opportunities. At Marvell, we’re driven by the belief that how we do things matters just as much as what we do. Because, with a foundation built on partnership, anything is possible.