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研发经理 西安紫光国芯半导体有限公司 西安 20-35万/年 06-21

学历要求:本科|工作经验:3-4年|公司性质:国企|公司规模:150-500人

负责评估以及终端产品整体研发工作;负责指导硬件系统设计;负责指导FW开发;负责系统问题分析解决方案;负责团队管理和任务分配。岗位要求:终端产品研发经理3年以上经验;熟悉存储器产品;沟通良好。

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销售(服务工程师) 海洋王照明科技股份有限公司 异地招聘 3-8千/月 06-10

学历要求:大专|工作经验:1年|公司性质:上市公司|公司规模:10000人以上

负责目标市场的照明产品、服务产品市场推广,项目运作和售后服务以达成销售目的;负责目标市场客户关系建立、维护;建立目标市场的客户档案信息及照明产品档案,承担所负责区域市场的照明产品售后服务工作。任职条件:大专及以上学历,专业不限;35岁以下;具有较强的团队协助意识、服务精神,能快速收集客户信息,建立关系;能适应长期派驻外地工作;具有较强的学习能力,抗压能力。诚邀优秀应届毕业生、退伍军人。薪酬待遇:试用期:综合工资2750-3810元/月+出差补助+销售提成+住宿+五险一金转正:综合工资3000-4330元/月+出差补助+销售提成+住宿+五险一金福利:员工福利:餐补+住宿+年功津贴+节日津贴+学历津贴+体检+蜜月旅游+购车补助等;员工子女福利:综合子女保险+子女抚养费+学杂费+暑期夏令营等;员工父母福利:医药费补助+体检+大病补助+高寿老人补助+父母过节费等。上班地点:福州市、南昌市、宁波市

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FPGA算法开发工程师 西安紫光国芯半导体有限公司 西安 1.2-1.5万/月 06-19

学历要求:本科|工作经验:1年|公司性质:国企|公司规模:150-500人

1、熟悉Verilog硬件描述语言,熟悉前端代码设计;2、熟悉xilinx FPGA器件及其集成开发环境,具备上板调试经验;3、熟悉FFT、FIR、Kingston变换等信息处理算法的优先,具备算法往FPGA移植能力; 4、熟悉DSP核使用优先;5、能够接受出差

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ASIC芯片验证工程师 西安紫光国芯半导体有限公司 西安 1.2-1.5万/月 06-19

学历要求:本科|工作经验:1年|公司性质:国企|公司规模:150-500人

1、熟悉SystemVerilog、Verilog等语言,熟悉UVM等验证方法学;2、熟悉IC设计和验证流程,熟练掌握EDA仿真工具的使用;3、搭建验证环境,完成模块级、系统级验证工作; 4、熟悉网络协议以及交换结构的优先;5、能够接受出差

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数字设计工程师 西安紫光国芯半导体有限公司 北京-海淀区 1.5-2.5万/月 06-19

学历要求:本科|工作经验:5-7年|公司性质:国企|公司规模:150-500人

RESPONSIBILITIES:· Work as IP design lead with potential grow to IP owner.· Work with SOC/IP architect, system engineering team, and SW/FW teams to create IP features and define micro-architecture for client/server/embedded SOC products.· Work on RTL Design implementation, LINT/CDC, Synthesis and Timing closure.· Work closely with SOC team to ensure IP delivery meets with requirements.· Work closely with SW, FW and system engineering teams on post-silicon bring-up/debug till production.· Participate in IP/Company’s methodology improvement, and new technology/architecture definition. REQUIREMENTS:· BSEE/MSEE with minimum of 6 years experiences in complex IP design with strong IP design knowledge/experience.· Excellent knowledge of Verilog, System Verilog and a scripting language; experience with Perl, Tcl and Ruby is a plus.· Solid x86 system architecture knowledge is a must, familiar with the traditional PC I/O interfaces especially in the area of PCIe.· One or more of the follow I/O IP design experiences is very helpful, Ethernet/PCIe/USB/SATA/NVME, etc.· The capability of understanding and analyzing I/O performance/power consumption based on IP design is necessary.· Working knowledge/experience with I/O SW driver and FW is a plus.· Security/cryptography knowledge is a plus· Strong analytical/problem solving skills and pronounced attention to details.· Self-motivated team player, and able to independently drive tasks to completion. · Strong and clear communication skill, fluent in English are required.

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IC验证工程师 西安紫光国芯半导体有限公司 北京-海淀区 1.5-2万/月 06-19

学历要求:本科|工作经验:2年|公司性质:国企|公司规模:150-500人

Responsibilities:1. According to the design specification, be responsible for the verification plan and verification objective definition.2. Test-bench development (modeling, assertions, checkers, monitors, score-board, regressions, coverage), test-case development (sequence, VRAD) and integration.3. Work with Random Verification methodology(VMM, OVM, UVM, eRM)4. Work as an independent verification engineers to check the design functionality at SOC module level and chip level.5. Work as interface with Front-End and Back-End engineer to optimize or review the design architecture and implementation.6. Verilog or VHDL coding according to design specification or external/internal IP integration.7. Support the post simulation with gate-level verilog or VHDL net list.Requirements:1. Either Bachelor, Master or PhD in Microelectronics, Electronic Engineering, or related field, 2+ Years of verification working experience.2. Experience with Verification language (SPECMAN/E-language, System-Verilog, Vera)3. Experience with RTL coding and simulators (Modelsim, NC-sim).4. Basic knowledge of script language (Perl, TCL, C-language and so on)5. Knowledge about 2G/3G/LTE handset baseband Architecture, ARM, AHB Architecture is a plus.6. Knowledge about Baseband chip peripheral (USB2.0/USB3.0, SSIC, MIPI) is a plus.7. Team oriented, love to work in young, international and highly motivated teams.8. Good command of English

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FAE工程师 西安紫光国芯半导体有限公司 上海-浦东新区 1-1.5万/月 06-19

学历要求:本科|工作经验:5-7年|公司性质:国企|公司规模:150-500人

工作职责:1. 为客户提供详细的设计技术支持;2. 协助销售和市场团队的工作;3. 可出差,加强客户之间关系;4. 根据客户及市场的需要,提供新产品开发的建议;5. 写技术报告,处理客户提出的问题;6. 为客户现场解决问题。要求:1. 电子工程/计算机工程/微电子学士或硕士学位,2年以上相关经验;2. 具有相关客户技术支持经验,以客户的服务为目的;3. 具备处理人际关系的技巧,以及团队精神和职业道德;4. 具备内存产品相关故障分析知识,处理示波器,逻辑分析仪和印刷电路板焊接工作技能;5. 良好的英文听、说、写、译能力及交流技巧; 6. 具有内存产品测试相关工作经验优先。

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DFV-Team Lead 西安紫光国芯半导体有限公司 上海-浦东新区 2.5-4万/月 06-19

学历要求:本科|工作经验:5-7年|公司性质:国企|公司规模:150-500人

Responsibilities:· Lead a team and perform project planning, estimation, tracking, mentoring, reviews, etc.· Work closely with the SoC design team on understanding the APU system features being designed;· Develop and execute test plans for system level functional features related to Memory Controller/ Power Management/ Coherency / Security / Multi-Media …etc.· Design, implement and improve verification testbench in Verilog, System-Verilog, C/C++ , UVM; · Develop and refine test libraries, model and test cases;· Apply functional coverage/assertion into testbench as enhancement;· Evaluation/review of all new or existing methods, comparing them to established procedures and standards both technical and non-technical and champion where applicable· Plan and conduct test centric Post Mortem evaluation/review· Develop and implement design quality control and improvement processes· Constantly look to improve design productivity· Leading the Team's development of leading edge innovative SOC/IP level features· Manage staff career development, goal planning and day-to-day problem resolution· Hands-on resolution of problems and priority calls· Carry milestone definition on complex ASIC/SoC designs - management of "gate" criteria· Resolve complex problems involving:§ advanced static timing analysis and formal verification§ RTL Linting and CDC checking§ ASIC/SoC Design flows and methodology implementations and enhancements§ IP/sub-system/SoC problemsRequirements:· Either Bachelor, Master or PhD in Microelectronics, Electronic Engineering, or related field 5+ years professional experience including SOC/PCIe/Fabrics/MMU Verification· Communication skills: excellent oral, written and presentation skills· Leadership experience in productivity improvement· Familiar with aspects of SOC/IP Design Goals and Milestones· Working knowledge of Verilog, System Verilog, C/C++, Perl/Python· At least 2 years of management experience with proven record of dealing with hiring, performance management and coaching of employees· Chipset and Fusion architecture and design knowledge (Northbridge, FCH, DDR Interface, Memory controllers,MMU)· DFT, Debug knowledge· Self-starter and quick learner and able to achieve successful outcomes in a non-hierarchical environment, with minimal supervision or direction· Detail oriented; ability to multitask through planning/organizing · Project management skills and experience

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数字设计工程师-SoC Design(DE) 西安紫光国芯半导体有限公司 西安 1-2万/月 06-19

学历要求:本科|工作经验:2年|公司性质:国企|公司规模:150-500人

Responsibilities:1. Module/block specification together with architect and other designers2. Module/block RTL Coding and system integration with verilog/VHDL3. Collaborate with verification engineers for module/block and system integration verification4. Collaborate with Physical design(Layout) engineers to ensure design meeting timing and area requirement5. Collaborate with DFT engineers for DFT feature6. Collaborate with FPGA engineers for prototype the designRequirements:1. Either Bachelor, Master or PhD in Microelectronics, Electronic Engineering, or related field, 2+ Years of design working experience.2. Experience in RTL coding(Verilog/VHDL) and logic synthesis3. Experience in simulators (Modelsim, NC-sim, VCS)4. Experience in Perl, or others scripting language5. Knowledge of 2G/3G/4G/5G baseband Architecture, ARM, AHB Architecture is a plus6. Knowledge of Baseband chip peripheral(PCIE/USB/MIPI/I2C) is a plus7. Good command of English

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数字后端工程师-Team Leader 西安紫光国芯半导体有限公司 西安 1.5-2万/月 06-19

学历要求:本科|工作经验:5-7年|公司性质:国企|公司规模:150-500人

Responsibilities:1. Responsible for technical management for team and leading team to finish BE tasks.2. Work as technical expert to support technical team.3. Responsible for developing digital designs with emphasis on backend, including Floor-plan, power planning, Place, CTS and Route.4. Work with Front-end designers to optimize timing/area/power of the design implementation and perform static timing analysis5. Optimization and Verification of layout for tape-out (including RC extraction, ECO, DRC, LVS).6. Power IR drop analysis and optimization, area and parasitic layout optimization, chip size optimization.7. Static Timing analysis (Prime Time) and setup/hold fix.8. Formal Verification for equivalence checking (Formality).9. Generation of fill structures according to technology requirements.Requirements:1. 1-3 years experience for technical team leadership.2. About 5 years experience in backend design flow (APR) with proven SOC tape-out experience.3. Experienced in Synopsys/Cadence automatically physical implementation tools and flows (IC-Compiler/ Astro / SOC-Encounter/ Milky-way/ Star-RCX) is a plus.4. Experience with one or more scripting languages (Perl, TCL, or Shell) to make reusable automatically flow is a plus.5. Experience and knowledge about FE design (RTL code, flow) and verification is a plus.6. Good communication in teamwork spirit.7. Good analytical and debugging skills.8. Good command of English.

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