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射频工程师 北京凌昆电磁技术有限公司 北京 1.5-2万/月 08-08

学历要求:硕士|工作经验:3-4年|公司性质:外资(欧美)|公司规模:150-500人

职位描述 Main responsibility: To do RF 2 designing of EMC chambers.To do system integration of wireless OTA testing solution package on site in China or Asia Region.To handle customer"training. "To support for RF issues on the project. To support sales department in RFfunction.Experience Requirements: Bachelor degree, Microwave, Radio,electronics or Telecom engineering background. 电子工程、微波、无线电专业,本科及以上学历。 Min.1 years working experience related field project. 有(一年及以上)相关项目经验。可以考虑优秀应届毕业生。 Familiar with EM/ Microwave/ Antenna theory. 熟悉电磁场 / 微波 / 天线理论。 Familiar with the application of equipment like Spectrum, VNA, etc. 熟悉电子通信领域常用仪器(频谱仪 , 矢量网络分析仪)。 Good English skill on both oral and written. 熟练的英文表达和写作能力。 Good IT skill, MS 2 office is a must. 熟练的电脑操作和办公软件运用。 Good communication skill and working under pressure with positive/dynamic thinking. 擅于与人交流,能够积极地思考并且能够承受工作压力。 Prefer to travel domestically or oversea. 能够经常出差工作。

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数字后端工程师-Team Leader 西安紫光国芯半导体有限公司 西安 1.5-2万/月 08-03

学历要求:本科|工作经验:5-7年|公司性质:国企|公司规模:150-500人

Responsibilities:1. Responsible for technical management for team and leading team to finish BE tasks.2. Work as technical expert to support technical team.3. Responsible for developing digital designs with emphasis on backend, including Floor-plan, power planning, Place, CTS and Route.4. Work with Front-end designers to optimize timing/area/power of the design implementation and perform static timing analysis5. Optimization and Verification of layout for tape-out (including RC extraction, ECO, DRC, LVS).6. Power IR drop analysis and optimization, area and parasitic layout optimization, chip size optimization.7. Static Timing analysis (Prime Time) and setup/hold fix.8. Formal Verification for equivalence checking (Formality).9. Generation of fill structures according to technology requirements.Requirements:1. 1-3 years experience for technical team leadership.2. About 5 years experience in backend design flow (APR) with proven SOC tape-out experience.3. Experienced in Synopsys/Cadence automatically physical implementation tools and flows (IC-Compiler/ Astro / SOC-Encounter/ Milky-way/ Star-RCX) is a plus.4. Experience with one or more scripting languages (Perl, TCL, or Shell) to make reusable automatically flow is a plus.5. Experience and knowledge about FE design (RTL code, flow) and verification is a plus.6. Good communication in teamwork spirit.7. Good analytical and debugging skills.8. Good command of English.

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System Support Engineering 西安紫光国芯半导体有限公司 上海-浦东新区 1-2万/月 08-03

学历要求:|工作经验:|公司性质:国企|公司规模:150-500人

Requirements: The candidate is preferred a Master degree in Electrical Engineering, Computer Science or English major. The candidate must be proficient in two or more of the following skill sets: 1. The candidate should have following experience/knowledge, such as computer structure, computer processor programming, Electrical Engineering.2. Have software/firmware/hardware background and could support software team to do driver integration. 3. The candidate should have analytical skill, such as reading, analyzing, converting technical information of internal design spec, support customer/software team for AMD southbridge product4. Nice to have experienced with LNUX Env (Perl, Tcl, etc.), build up block level verification ENV for FPGA/ASIC chip validation.5. design verification experience, should be versatile in any one of the high-level verification flow such as SV, VMM, OVM, UVM etc. as well as knowledge of industry standard tools for verification6. Have on board/FPGA/post-silicon validation is plus, good at English reading and writing. Responsibility: As a System Support Engineering, you will acquire solid knowledge about complex product information of AMD’s key IC products. You work as a AMD IP validation owner, need to author and publish AMD technical information in the manner of easy to use, easy to understand, and easy to find. You will work closely with different AMD function teams including product management, design, software, development, testing, and involve in chip Bring-up activity. You develop complex, in-depth communications for internal and external audiences and manage projects that involve worldwide teams.

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CIP-Nfeint 西安紫光国芯半导体有限公司 上海-浦东新区 1-2万/月 08-03

学历要求:|工作经验:|公司性质:国企|公司规模:150-500人

RESPONSIBILITIES:Responsible for IP level Synthesis/Formal/STA check.Responsible for IP level LINT/CDC/VSI check.Responsible for IP level regularly regression.Responsible for function ECO implementation and LEC/DRC check.Work with front-end integration team and physical design team on timing closure.· Co-ordinating design and implementation activities.· REQUIREMENTS:· Minimum 1 years of experience with Verilog a MUST.Familiar with front-end design flow.Experience on synthesis, timing analysis and formal verification.· Excellent knowledge of verilog and a scripting language; experience with Perl and TCL is a plus.· Low power experience is an asset.· Strong analytical/problem solving skills and pronounced attention to details.· Must be a self starter, and able to independently drive tasks to completion.· Strong interpersonal and communication skillsStrong responsibilities and team spirit.· EDUCATION: · Bachelor, Master's degree in Electrical or Computer engineering.

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存储终端产品研发经理 西安紫光国芯半导体有限公司 西安 20-35万/年 08-03

学历要求:本科|工作经验:5-7年|公司性质:国企|公司规模:150-500人

岗位职责:1、 负责存储相关终端产品的架构设计和功能开发,联合软硬件设计人员进行系统集成与调试;2、管理硬件团队,完成硬件部分的总体架构方案,包括器件选型、原理图设计、指导PCB Layout、调试等工作;3、协调Firmware团队,完成Embedded固件开发,能够参与指导定义单板上嵌入式软件的功能、接口,并规划软件方案;4、对产品开发过程中遇到的问题及时组织讨论、分析给出解决方案;5、对产品的进度和质量负责,处理市场反馈的各种信息,协调内部、外部资源保障产品的成功上市。任职资格:1、 通信、电子、微电子、计算机等相关专业, 5年以上存储器相关产品的设计经验;2、 精通存储产品系统设计,调试,测试和不良分析;3、 精通硬件产品设计,能制定硬件设计、选型、流程规范及新产品的堆叠、物料选型、风险评估;4、 熟悉Embedded固件开发,系统整合,熟悉C语言使用和嵌入式软件/固件;5、 熟悉NVDIMM,SSD电路的优先;5、熟悉产品设计开发流程,有良好的团队管理经历,具有独立分析解决产品设计中遇到问题的能力; 6、有良好的沟通技巧,积极主动,拼搏进取,自学能力较好。

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FPGA算法开发工程师 西安紫光国芯半导体有限公司 西安 1.2-1.5万/月 08-03

学历要求:本科|工作经验:1年|公司性质:国企|公司规模:150-500人

1、熟悉Verilog硬件描述语言,熟悉前端代码设计;2、熟悉xilinx FPGA器件及其集成开发环境,具备上板调试经验;3、熟悉FFT、FIR、Kingston变换等信息处理算法的优先,具备算法往FPGA移植能力; 4、熟悉DSP核使用优先;5、能够接受出差

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ASIC芯片验证工程师 西安紫光国芯半导体有限公司 西安 1.2-1.5万/月 08-03

学历要求:本科|工作经验:1年|公司性质:国企|公司规模:150-500人

1、熟悉SystemVerilog、Verilog等语言,熟悉UVM等验证方法学;2、熟悉IC设计和验证流程,熟练掌握EDA仿真工具的使用;3、搭建验证环境,完成模块级、系统级验证工作; 4、熟悉网络协议以及交换结构的优先;5、能够接受出差

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数字后端工程师 西安紫光国芯半导体有限公司 北京-海淀区 1.5-2万/月 08-03

学历要求:本科|工作经验:2年|公司性质:国企|公司规模:150-500人

Responsibilities:1. Responsible for Synthesis, timing closure2. Responsible for developing digital designs with emphasis on backend, including Floor-plan, power planning, Place, CTS and Route. 3. Work with Front-end designers to optimize timing/area/power of the design implementation and perform static timing analysis.4. Optimization and Verification of layout for tape-out (including RC extraction, ECO, DRC, LVS).5. Power IR drop analysis and optimization, area and parasitic layout optimization, chip size optimization.6. Static Timing analysis (Prime Time) and setup/hold fix.7. Formal Verification for equivalence checking (Formality).8. Generation of fill structures according to technology requirements.Requirements:1. 2-4 years experience in backend design flow (APR) with proven SOC tape-out experience.2. RTL(verilog) coding and style checking3. Scripts based on makefile, perl, TCL or csh/tcsh 4. Clock-domain-cross checking 5. Logic synthesis or physical Synthesis(Design Compiler)6. Static timing analysis (Primetime)7. Experienced in Synopsys/Cadence automatically physical implementation tools and flows (IC-Compiler/ Astro / SOC-Encounter/ Milky-way/ Star-RCX) is a plus.8. Experience with one or more scripting languages (Perl, TCL, or Shell) to make reusable automatically flow is a plus.9. Experience and knowledge about FE design (RTL code, flow) and verification is a plus.10. Good analytical and debugging skills.11. Good command of English.

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DFT-可测性设计工程师 西安紫光国芯半导体有限公司 北京-海淀区 1.5-2万/月 08-03

学历要求:本科|工作经验:2年|公司性质:国企|公司规模:150-500人

Responsibilities:1. Participate in SoC level DFT architecture definition.2. Implement DFT strategy for the SoC chips, cooperating with design team3. Implement basic DFT schemes, including scan, boundary scan, Mem BIST and Logic BIST.4. Develop the high coverage and cost effective test patterns.5. Verify all DFT logics and test patterns with simulation and static timing analysis tool.6. Support other teams for DFT related problems.Requirements:1. Either Bachelor or Master degree, 2+ years related experience required.2. Basic knowledge of IC design flow, including coding, simulation, verification, synthesis and STA3. Good understanding of the General DFT methodology such as BIST, SCAN, JTAG and ATPG.4. Knowledge on and familiar with basic Mentor/ Synopsys DFT flow and tools5. Proficient in Verilog/VHDL language6. Be familiar with Shell/TCL/Perl program, or skilled in C program7. Good English communication skills8. Self-motivated and good team player

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验证工程师-SoC Function Verification(FV) 西安紫光国芯半导体有限公司 西安 1-2万/月 08-03

学历要求:|工作经验:3-4年|公司性质:国企|公司规模:150-500人

Responsibilities:1. Verify design and implementation at module/subsystem/chip level2. Define verification scope and develop verification plan/objective according to specification3. Test-bench development in using random verification methodologies such as UVM, test case development4. Collaborate with architects, designer and physical design(layout) for implementation5. Work for post simulation with gate-level netlist6. Support pre/post silicon testRequirements:1. Either Bachelor, Master or PhD in Microelectronics, Electronic Engineering, or related field, 2+ Years of verification working experience2. Experience in System-Verilog/UVM/OVM/VMM/Specman-E3. Experience in simulators (Modelsim, NC-sim, VCS)4. Experience in Perl or others scripting language5. Knowledge of 2G/3G/4G/5G baseband Architecture, ARM, AHB Architecture is a plus6. Knowledge of Baseband chip peripheral(PCIE/USB/MIPI/I2C) is a plus7. Good command of English

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