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System Support Engineering 西安紫光国芯半导体有限公司 上海-浦东新区 1-2万/月 10-19

学历要求:|工作经验:|公司性质:国企|公司规模:150-500人

Requirements: The candidate is preferred a Master degree in Electrical Engineering, Computer Science or English major. The candidate must be proficient in two or more of the following skill sets: 1. The candidate should have following experience/knowledge, such as computer structure, computer processor programming, Electrical Engineering.2. Have software/firmware/hardware background and could support software team to do driver integration. 3. The candidate should have analytical skill, such as reading, analyzing, converting technical information of internal design spec, support customer/software team for AMD southbridge product4. Nice to have experienced with LNUX Env (Perl, Tcl, etc.), build up block level verification ENV for FPGA/ASIC chip validation.5. design verification experience, should be versatile in any one of the high-level verification flow such as SV, VMM, OVM, UVM etc. as well as knowledge of industry standard tools for verification6. Have on board/FPGA/post-silicon validation is plus, good at English reading and writing. Responsibility: As a System Support Engineering, you will acquire solid knowledge about complex product information of AMD’s key IC products. You work as a AMD IP validation owner, need to author and publish AMD technical information in the manner of easy to use, easy to understand, and easy to find. You will work closely with different AMD function teams including product management, design, software, development, testing, and involve in chip Bring-up activity. You develop complex, in-depth communications for internal and external audiences and manage projects that involve worldwide teams.

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管理部经理(生产/销售/库存企划) 上海日弘企业管理咨询有限公司 上海 1.5-2万/月 10-21

学历要求:本科|工作经验:5-7年|公司性质:合资|公司规模:少于50人

担当业务:管理职業務:-中国轮胎事业全部的需求管理实施、生产/销售/库存的最优化、建立起时刻满足所需量并提供优惠价格的体制-现下情况的把握以及今后预测相关情报的收集分析,解决需求供给之间差异,制定策略并通过与相关部门的联系协助,实施推进   -面向合规管理,SCM业务要领,权限规定的整备以及对于下属理解的定期教育,业务流程等确认检查等"任职要求相关实务经验者本科以上学历,日语熟练,年龄不限,按以下优先顺序1.SCM企画/管理业务经验2.生产企画/管理业务经验"员工福利"1、有商业医疗保险(子女保险)2、每年1次公司旅游,不定期组织公司活动3、午餐补贴、交通补贴、通讯补贴、日语津贴4、各类节日费"

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ASIC芯片设计工程师 西安紫光国芯半导体有限公司 西安 1.2-1.5万/月 10-19

学历要求:本科|工作经验:1年|公司性质:国企|公司规模:150-500人

1、根据设计目标的功能、性能要求,采用Verilog语言进行代码设计;2、对RTL逻辑代码进行仿真,验证功能正确性; 3、能独立开展编码与调试、上板测试调试任务、有以太网技术背景与逻辑开发经验优先;4、能够接受出差

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数字设计工程师 西安紫光国芯半导体有限公司 北京-海淀区 1.5-2.5万/月 10-19

学历要求:本科|工作经验:5-7年|公司性质:国企|公司规模:150-500人

RESPONSIBILITIES:· Work as IP design lead with potential grow to IP owner.· Work with SOC/IP architect, system engineering team, and SW/FW teams to create IP features and define micro-architecture for client/server/embedded SOC products.· Work on RTL Design implementation, LINT/CDC, Synthesis and Timing closure.· Work closely with SOC team to ensure IP delivery meets with requirements.· Work closely with SW, FW and system engineering teams on post-silicon bring-up/debug till production.· Participate in IP/Company’s methodology improvement, and new technology/architecture definition. REQUIREMENTS:· BSEE/MSEE with minimum of 6 years experiences in complex IP design with strong IP design knowledge/experience.· Excellent knowledge of Verilog, System Verilog and a scripting language; experience with Perl, Tcl and Ruby is a plus.· Solid x86 system architecture knowledge is a must, familiar with the traditional PC I/O interfaces especially in the area of PCIe.· One or more of the follow I/O IP design experiences is very helpful, Ethernet/PCIe/USB/SATA/NVME, etc.· The capability of understanding and analyzing I/O performance/power consumption based on IP design is necessary.· Working knowledge/experience with I/O SW driver and FW is a plus.· Security/cryptography knowledge is a plus· Strong analytical/problem solving skills and pronounced attention to details.· Self-motivated team player, and able to independently drive tasks to completion. · Strong and clear communication skill, fluent in English are required.

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IC验证工程师 西安紫光国芯半导体有限公司 北京-海淀区 1.5-2万/月 10-19

学历要求:本科|工作经验:2年|公司性质:国企|公司规模:150-500人

Responsibilities:1. According to the design specification, be responsible for the verification plan and verification objective definition.2. Test-bench development (modeling, assertions, checkers, monitors, score-board, regressions, coverage), test-case development (sequence, VRAD) and integration.3. Work with Random Verification methodology(VMM, OVM, UVM, eRM)4. Work as an independent verification engineers to check the design functionality at SOC module level and chip level.5. Work as interface with Front-End and Back-End engineer to optimize or review the design architecture and implementation.6. Verilog or VHDL coding according to design specification or external/internal IP integration.7. Support the post simulation with gate-level verilog or VHDL net list.Requirements:1. Either Bachelor, Master or PhD in Microelectronics, Electronic Engineering, or related field, 2+ Years of verification working experience.2. Experience with Verification language (SPECMAN/E-language, System-Verilog, Vera)3. Experience with RTL coding and simulators (Modelsim, NC-sim).4. Basic knowledge of script language (Perl, TCL, C-language and so on)5. Knowledge about 2G/3G/LTE handset baseband Architecture, ARM, AHB Architecture is a plus.6. Knowledge about Baseband chip peripheral (USB2.0/USB3.0, SSIC, MIPI) is a plus.7. Team oriented, love to work in young, international and highly motivated teams.8. Good command of English

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验证工程师-SoC Function Verification(FV) 西安紫光国芯半导体有限公司 西安 1-2万/月 10-19

学历要求:|工作经验:3-4年|公司性质:国企|公司规模:150-500人

Responsibilities:1. Verify design and implementation at module/subsystem/chip level2. Define verification scope and develop verification plan/objective according to specification3. Test-bench development in using random verification methodologies such as UVM, test case development4. Collaborate with architects, designer and physical design(layout) for implementation5. Work for post simulation with gate-level netlist6. Support pre/post silicon testRequirements:1. Either Bachelor, Master or PhD in Microelectronics, Electronic Engineering, or related field, 2+ Years of verification working experience2. Experience in System-Verilog/UVM/OVM/VMM/Specman-E3. Experience in simulators (Modelsim, NC-sim, VCS)4. Experience in Perl or others scripting language5. Knowledge of 2G/3G/4G/5G baseband Architecture, ARM, AHB Architecture is a plus6. Knowledge of Baseband chip peripheral(PCIE/USB/MIPI/I2C) is a plus7. Good command of English

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晶圆产品测试工程师 西安紫光国芯半导体有限公司 西安 1-1.5万/月 10-19

学历要求:本科|工作经验:2年|公司性质:国企|公司规模:150-500人

Responsibilities:1. Memory product (IC) test definition, test program development and test flow maintenance.2. Hands-on experience, programming and execution of test/test-flows on Memory testers (Advantest T5571/T5377, etc).3. Perform program debugging, failure analysis, root cause finding, and yield analysis4. Test coverage development and test time optimization during product development and production test maintenance.5. Perform design verification by Verilog/Ananosim simulations6. Repair analysis by certain calculation method. 7. Assist on the definition and specification for probecard design.Requirements: 1. Master or PhD degree in Computer Science, Electrical and Electronic Engineering, or relevant.2. Basic knowledge in semiconductor physics, integrated circuits, and IC process technologies.3. Familiar with UNIX or Solaris system 4. Experience in DRAM/NAND Flash test and analysis or DRAM/Flash tester programming (Advantest and Verigy) is desired.5. Solid Programming skills (C, C++, Perl, etc) is highly preferred,6. Familiar with date analysis tool(JMP) or date programmer software(VBA) base on the excel is a plus.7. Interested in working in a lab-environment and conducting hands-on measurements (memory tester, oscilloscope, logic analyzer, etc).8. Highly motivated and engaged, independent problem solving skills, good communication and presentation skills.9. Willing to work under pressure, willing to travel.10. English language skill in writing and speaking is a must.

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存储产品FAE 西安紫光国芯半导体有限公司 西安 15-30万/年 10-19

学历要求:本科|工作经验:|公司性质:国企|公司规模:150-500人

职责描述:1.根据emmc/UFS/flash产品应用环境的不同,编写测试emmc/UFS/flash产品的测试程序;其中应用环境包括ARM,安卓,或国产CPU和传统X86架构系统等;根据DRAM/flash产品的特点来制定满足客户规范的系统级测试方案,并执行测试方案;2.根据公司项目或者客户的需求,不断的优化和改进emmc/UFS/flash产品的测试程序,以提高产品测试效率和覆盖率;根据客户的需求来不断的优化和改进emmc/UFS/flash系统级应用测试方案;3.执行产品的系统级测试方案,和不同部门以及项目负责人良好合作,及时反馈产品可能在设计、晶圆和产品终测中出现的问题,并协助各相关部门解决测试中的问题;分析公司产品在各种平台应用中(计算机、服务器、嵌入式系统等)出现的技术问题,协助提高产品测试覆盖率;4.制定产品的规格书以及客户需要的相关文档等;和不同部门以及项目负责人良好合作,协助各相关部门解决测试中的问题;5.在应用测试中观察和反馈产品可能在设计、晶圆和产品终测中出现的问题;6.制定产品的规格书以及客户需要的相关文档。技术要求:1.在半导体相关行业公司工作3年以上的研究生或者本科生, 计算机或者电子专业;2.熟练掌握计算机系统相关的知识包括主板、CPU、芯片组和操作系统等;3.编程语言的掌握:(1) 熟练掌握C/C++语言,有丰富的编程经验;熟悉汇编语言;(2) 有ARM或安卓系统的底层驱动程序开发的相关经验;(3) 对FPGA有一定的了解,有一定的VHDL编程经验;4.了解半导体相关的知识包括工艺和电路等;5.熟练掌握测试设备包括示波器和逻辑分析仪;6.了解计算机编程语言包括C和汇编语言;7.有良好的英语口语和书写能力;8.能够独立完成工作并解决问题;9.能够跨部门协作工作。

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Design for Test Engineer (DFT) 西安紫光国芯半导体有限公司 异地招聘 20-45万/年 10-19

学历要求:本科|工作经验:|公司性质:国企|公司规模:150-500人

以下招聘职位均为公司设计服务部门的工程师职位,为上海大型国际IC公司以及国内顶端IC公司提供on-site设计服务。西安紫光国芯的设计服务部门能够提供高端设计服务,具备从设计规格到芯片流片完整流程的设计经验,包括:设计实现、功能验证、综合和DFT、物理实现、时序和物理检查、流片。公司在过去几年中成功为客户完成了十几款SoC在65nm/40nm/28nm/14nm工艺上的SoC芯片设计和流片,帮助客户低成本的、高效的实现产品化,是目前国内最大的设计服务外包服务商,所服务的客户均为国际知名大型芯片设计公司以及国内顶端芯片设计公司,具备一流的技术及设计环境以及良好的文化氛围,我们的员工在客户端承担核心技术板块,使其可以快速稳定成长。 我们各个业务板块均提供先进的设计开发环境,良好的企业文化以及人文关怀,优厚的薪酬待遇,完善的休假体系,全面的社会及商业保险。诚邀有志IC事业的人才加盟共同发展!Responsibilities:1. Participate in SoC level DFT architecture definition.2. Implement DFT strategy for the SoC chips, cooperating with design team3. Implement basic DFT schemes, including scan, boundary scan, Mem BIST and Logic BIST.4. Develop the high coverage and cost effective test patterns.5. Verify all DFT logics and test patterns with simulation and static timing analysis tool.6. Support other teams for DFT related problems.Requirements:1. Either Bachelor or Master degree, 2+ years related experience required.2. Basic knowledge of IC design flow, including coding, simulation, verification, synthesis and STA3. Good understanding of the General DFT methodology such as BIST, SCAN, JTAG and ATPG.4. Knowledge on and familiar with basic Mentor/ Synopsys DFT flow and tools5. Proficient in Verilog/VHDL language6. Be familiar with Shell/TCL/Perl program, or skilled in C program7. Good English communication skills8. Self-motivated and good team player

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集成电路测试工程师(设计分析与验证) 西安紫光国芯半导体有限公司 西安 15-25万/年 10-19

学历要求:本科|工作经验:|公司性质:国企|公司规模:150-500人

Responsibilities: 1. Design verification and analysis of new Memory products. 2. Simulations and analyses together with responsible circuit designers, correlation of simulation-data versus measurement. 3. Hands on definition, programming and execution of test/test-flows on Memory analysis testers (V93k, HP95k, Mosaid). 4. Setting up engineering-environments specific to certain tasks and adjust set-up frequently, work with oscilloscopes, TDR, etc. 5. Perform electrical characterization of parameters specified in the data sheet 6. Verify functionality and performance of all DfT-features of a memory product, work with design and production test to identify problems 7. Support of (Field) Application Engineers to identify and analyze problems at the end-customer 8. Definition and specification for product-specific tester-hardware (load-boards, probe-cards, etc.) Requirements: 1. Either Master or PhD in Computer Science, Electrical Engineering, or related field Experience, Knowledge. 2. Semiconductor device physics, circuit design and basic layout know how is a must. 3. Have Unix skills and Basic Programming skills (preferably C++, Perl) 4. Experience and interest to work in a lab-environment and do hands-on electrical measurements (memory-tester, oscilloscope, pico-probing, etc), setup and debug 5. High frequency measurement know how is desired. 6. Experience in DRAM test and analysis or DRAM tester programming (V93k, HP95k, Mosaid) is desirable. 7.Highly motivated and engaged, love to find tackle and solve new problems. 8. Good communication and presentation skills. 9. English language skill in writing and speaking is a must. HR Email:hr-xian@scsemicon.com

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