• EN
|

招聘信息 | 企业服务

您所在的位置:最新招聘信息 >全国职位信息
更多:

已选条件:
子女保险 电子技术/半导体/集成电路
清除条件
全选
申请职位

资深品质工程师 西安紫光国芯半导体有限公司 西安 0.8-1.2万/月 03-22

学历要求:本科|工作经验:3-4年|公司性质:国企|公司规模:150-500人

工作职责:制定Memory产品(Flash/eMMC/eMCP/UFS/SSD)品质控制方案,监控产品良率,监控来料、生产制程品质和产品出厂品质;生产过程半成品、产成品品质异常处理;协同研发、工艺整合、可靠性工程、失效分析和客诉处理部门,提升产品良率,持续品质提升,达成客户品质要求;定期与供应商评估产品品质表现,驱动代工厂改善产品良率和品质;定期向管理层汇报产品良率及品质表现。任职资格:1.专业:本科以上、研究生优先, 半导体/微电子/电子/电气工程/自动化/通讯工程专业优先;2.专业经验: 半导体类公司三年以上从业经验;有Flash、eMMC、eMCP、SSD或者DRAM经验者优先;有晶圆厂/封测厂工作经验者优先;3. 熟悉半导体制造工艺、SPC管控、统计分析工具和软件;有一定的编程能力(R/Python/VB);4. 外语水平: 英文流利,英语4级或以上者优先,具有外企或境外相关行业工作经验者优先; 5 个人品质: 良好的组织沟通协调能力、工作细致认真,谨慎细心,条理性强、责任心强,勇于承担挑战性的工作、具有开拓精神和团队精神。

立即申请
收藏

资深品质工程师 西安紫光国芯半导体有限公司 异地招聘 0.8-1.2万/月 03-22

学历要求:本科|工作经验:3-4年|公司性质:国企|公司规模:150-500人

工作职责:制定Memory产品(Flash/eMMC/eMCP/UFS/SSD)品质控制方案,监控产品良率,监控来料、生产制程品质和产品出厂品质;生产过程半成品、产成品品质异常处理;协同研发、工艺整合、可靠性工程、失效分析和客诉处理部门,提升产品良率,持续品质提升,达成客户品质要求;定期与供应商评估产品品质表现,驱动代工厂改善产品良率和品质;定期向管理层汇报产品良率及品质表现。任职资格:1.专业:本科以上、研究生优先, 半导体/微电子/电子/电气工程/自动化/通讯工程专业优先;2.专业经验: 半导体类公司三年以上从业经验;有Flash、eMMC、eMCP、SSD或者DRAM经验者优先;有晶圆厂/封测厂工作经验者优先;3. 熟悉半导体制造工艺、SPC管控、统计分析工具和软件;有一定的编程能力(R/Python/VB);4. 外语水平: 英文流利,英语4级或以上者优先,具有外企或境外相关行业工作经验者优先; 5 个人品质: 良好的组织沟通协调能力、工作细致认真,谨慎细心,条理性强、责任心强,勇于承担挑战性的工作、具有开拓精神和团队精神。

立即申请
收藏

资深品质工程师 西安紫光国芯半导体有限公司 异地招聘 0.8-1.2万/月 03-22

学历要求:本科|工作经验:3-4年|公司性质:国企|公司规模:150-500人

工作职责:制定Memory产品(Flash/eMMC/eMCP/UFS/SSD)品质控制方案,监控产品良率,监控来料、生产制程品质和产品出厂品质;生产过程半成品、产成品品质异常处理;协同研发、工艺整合、可靠性工程、失效分析和客诉处理部门,提升产品良率,持续品质提升,达成客户品质要求;定期与供应商评估产品品质表现,驱动代工厂改善产品良率和品质;定期向管理层汇报产品良率及品质表现。任职资格:1.专业:本科以上、研究生优先, 半导体/微电子/电子/电气工程/自动化/通讯工程专业优先;2.专业经验: 半导体类公司三年以上从业经验;有Flash、eMMC、eMCP、SSD或者DRAM经验者优先;有晶圆厂/封测厂工作经验者优先;3. 熟悉半导体制造工艺、SPC管控、统计分析工具和软件;有一定的编程能力(R/Python/VB);4. 外语水平: 英文流利,英语4级或以上者优先,具有外企或境外相关行业工作经验者优先; 5 个人品质: 良好的组织沟通协调能力、工作细致认真,谨慎细心,条理性强、责任心强,勇于承担挑战性的工作、具有开拓精神和团队精神。

立即申请
收藏

资深品质工程师 西安紫光国芯半导体有限公司 异地招聘 0.8-1.2万/月 03-22

学历要求:本科|工作经验:3-4年|公司性质:国企|公司规模:150-500人

制定Memory产品(Flash/eMMC/eMCP/UFS/SSD)品质控制方案,监控产品良率,监控来料、生产制程品质和产品出厂品质;生产过程半成品、产成品品质异常处理;协同研发、工艺整合、可靠性工程、失效分析和客诉处理部门,提升产品良率,持续品质提升,达成客户品质要求;定期与供应商评估产品品质表现,驱动代工厂改善产品良率和品质;定期向管理层汇报产品良率及品质表现。任职资格:1.专业:本科以上、研究生优先, 半导体/微电子/电子/电气工程/自动化/通讯工程专业优先;2.专业经验: 半导体类公司三年以上从业经验;有Flash、eMMC、eMCP、SSD或者DRAM经验者优先;有晶圆厂/封测厂工作经验者优先;3. 熟悉半导体制造工艺、SPC管控、统计分析工具和软件;有一定的编程能力(R/Python/VB);4. 外语水平: 英文流利,英语4级或以上者优先,具有外企或境外相关行业工作经验者优先; 5 个人品质: 良好的组织沟通协调能力、工作细致认真,谨慎细心,条理性强、责任心强,勇于承担挑战性的工作、具有开拓精神和团队精神。

立即申请
收藏

资深品质工程师 西安紫光国芯半导体有限公司 异地招聘 0.8-1.2万/月 03-22

学历要求:本科|工作经验:3-4年|公司性质:国企|公司规模:150-500人

制定Memory产品(Flash/eMMC/eMCP/UFS/SSD)品质控制方案,监控产品良率,监控来料、生产制程品质和产品出厂品质;生产过程半成品、产成品品质异常处理;协同研发、工艺整合、可靠性工程、失效分析和客诉处理部门,提升产品良率,持续品质提升,达成客户品质要求;定期与供应商评估产品品质表现,驱动代工厂改善产品良率和品质;定期向管理层汇报产品良率及品质表现。任职资格:1.专业:本科以上、研究生优先, 半导体/微电子/电子/电气工程/自动化/通讯工程专业优先;2.专业经验: 半导体类公司三年以上从业经验;有Flash、eMMC、eMCP、SSD或者DRAM经验者优先;有晶圆厂/封测厂工作经验者优先;3. 熟悉半导体制造工艺、SPC管控、统计分析工具和软件;有一定的编程能力(R/Python/VB);4. 外语水平: 英文流利,英语4级或以上者优先,具有外企或境外相关行业工作经验者优先; 5 个人品质: 良好的组织沟通协调能力、工作细致认真,谨慎细心,条理性强、责任心强,勇于承担挑战性的工作、具有开拓精神和团队精神。

立即申请
收藏

资深品质工程师 西安紫光国芯半导体有限公司 西安 0.8-1.2万/月 03-22

学历要求:本科|工作经验:3-4年|公司性质:国企|公司规模:150-500人

制定Memory产品(Flash/eMMC/eMCP/UFS/SSD)品质控制方案,监控产品良率,监控来料、生产制程品质和产品出厂品质;生产过程半成品、产成品品质异常处理;协同研发、工艺整合、可靠性工程、失效分析和客诉处理部门,提升产品良率,持续品质提升,达成客户品质要求;定期与供应商评估产品品质表现,驱动代工厂改善产品良率和品质;定期向管理层汇报产品良率及品质表现。任职资格:1.专业:本科以上、研究生优先, 半导体/微电子/电子/电气工程/自动化/通讯工程专业优先;2.专业经验: 半导体类公司三年以上从业经验;有Flash、eMMC、eMCP、SSD或者DRAM经验者优先;有晶圆厂/封测厂工作经验者优先;3. 熟悉半导体制造工艺、SPC管控、统计分析工具和软件;有一定的编程能力(R/Python/VB);4. 外语水平: 英文流利,英语4级或以上者优先,具有外企或境外相关行业工作经验者优先; 5 个人品质: 良好的组织沟通协调能力、工作细致认真,谨慎细心,条理性强、责任心强,勇于承担挑战性的工作、具有开拓精神和团队精神。

立即申请
收藏

Flash设计工程师 西安紫光国芯半导体有限公司 西安 15-30万/年 03-22

学历要求:硕士|工作经验:1年|公司性质:国企|公司规模:150-500人

岗位职责:1.    进行Flash产品的研发,负责相关电路的设计、验证和评估。2.    负责芯片性能分析和问题调试任职要求:1.    微电子等相关专业,硕士及以上学历 2.    了解半导体器件原理和工艺流程 3.    熟练使用VIRTUOSO、HSPICE等IC全定制设计工具 4.    具有FLASH/EEPROM设计经验5.    具有良好的学习、分析能力6.    具有良好的沟通能力和团队合作能力 7.    对SRAM/DRAM等存储器有了解者优先

立即申请
收藏

ASIC芯片设计工程师 西安紫光国芯半导体有限公司 西安 15-25万/年 03-22

学历要求:本科|工作经验:1年|公司性质:国企|公司规模:150-500人

1、根据设计目标的功能、性能要求,采用Verilog语言进行代码设计;2、对RTL逻辑代码进行仿真,验证功能正确性; 3、能独立开展编码与调试、上板测试调试任务、有以太网技术背景与逻辑开发经验优先;4、能够接受出差

立即申请
收藏

数字设计工程师 西安紫光国芯半导体有限公司 北京-海淀区 15-30万/年 03-22

学历要求:本科|工作经验:3-4年|公司性质:国企|公司规模:150-500人

RESPONSIBILITIES:· Work as IP design lead with potential grow to IP owner.· Work with SOC/IP architect, system engineering team, and SW/FW teams to create IP features and define micro-architecture for client/server/embedded SOC products.· Work on RTL Design implementation, LINT/CDC, Synthesis and Timing closure.· Work closely with SOC team to ensure IP delivery meets with requirements.· Work closely with SW, FW and system engineering teams on post-silicon bring-up/debug till production.· Participate in IP/Company’s methodology improvement, and new technology/architecture definition. REQUIREMENTS:· BSEE/MSEE with minimum of 6 years experiences in complex IP design with strong IP design knowledge/experience.· Excellent knowledge of Verilog, System Verilog and a scripting language; experience with Perl, Tcl and Ruby is a plus.· Solid x86 system architecture knowledge is a must, familiar with the traditional PC I/O interfaces especially in the area of PCIe.· One or more of the follow I/O IP design experiences is very helpful, Ethernet/PCIe/USB/SATA/NVME, etc.· The capability of understanding and analyzing I/O performance/power consumption based on IP design is necessary.· Working knowledge/experience with I/O SW driver and FW is a plus.· Security/cryptography knowledge is a plus· Strong analytical/problem solving skills and pronounced attention to details.· Self-motivated team player, and able to independently drive tasks to completion. · Strong and clear communication skill, fluent in English are required.

立即申请
收藏

IC验证工程师 西安紫光国芯半导体有限公司 北京-海淀区 17-30万/年 03-22

学历要求:本科|工作经验:3-4年|公司性质:国企|公司规模:150-500人

Responsibilities:1. According to the design specification, be responsible for the verification plan and verification objective definition.2. Test-bench development (modeling, assertions, checkers, monitors, score-board, regressions, coverage), test-case development (sequence, VRAD) and integration.3. Work with Random Verification methodology(VMM, OVM, UVM, eRM)4. Work as an independent verification engineers to check the design functionality at SOC module level and chip level.5. Work as interface with Front-End and Back-End engineer to optimize or review the design architecture and implementation.6. Verilog or VHDL coding according to design specification or external/internal IP integration.7. Support the post simulation with gate-level verilog or VHDL net list.Requirements:1. Either Bachelor, Master or PhD in Microelectronics, Electronic Engineering, or related field, 2+ Years of verification working experience.2. Experience with Verification language (SPECMAN/E-language, System-Verilog, Vera)3. Experience with RTL coding and simulators (Modelsim, NC-sim).4. Basic knowledge of script language (Perl, TCL, C-language and so on)5. Knowledge about 2G/3G/LTE handset baseband Architecture, ARM, AHB Architecture is a plus.6. Knowledge about Baseband chip peripheral (USB2.0/USB3.0, SSIC, MIPI) is a plus.7. Team oriented, love to work in young, international and highly motivated teams.8. Good command of English

立即申请
收藏

数字设计工程师-SoC Design(DE) 西安紫光国芯半导体有限公司 西安 17-25万/年 03-22

学历要求:本科|工作经验:2年|公司性质:国企|公司规模:150-500人

Responsibilities:1. Module/block specification together with architect and other designers2. Module/block RTL Coding and system integration with verilog/VHDL3. Collaborate with verification engineers for module/block and system integration verification4. Collaborate with Physical design(Layout) engineers to ensure design meeting timing and area requirement5. Collaborate with DFT engineers for DFT feature6. Collaborate with FPGA engineers for prototype the designRequirements:1. Either Bachelor, Master or PhD in Microelectronics, Electronic Engineering, or related field, 2+ Years of design working experience.2. Experience in RTL coding(Verilog/VHDL) and logic synthesis3. Experience in simulators (Modelsim, NC-sim, VCS)4. Experience in Perl, or others scripting language5. Knowledge of 2G/3G/4G/5G baseband Architecture, ARM, AHB Architecture is a plus6. Knowledge of Baseband chip peripheral(PCIE/USB/MIPI/I2C) is a plus7. Good command of English

立即申请
收藏

晶圆产品测试工程师 西安紫光国芯半导体有限公司 西安 17-25万/年 03-22

学历要求:本科|工作经验:2年|公司性质:国企|公司规模:150-500人

Responsibilities:1. Memory product (IC) test definition, test program development and test flow maintenance.2. Hands-on experience, programming and execution of test/test-flows on Memory testers (Advantest T5571/T5377, etc).3. Perform program debugging, failure analysis, root cause finding, and yield analysis4. Test coverage development and test time optimization during product development and production test maintenance.5. Perform design verification by Verilog/Ananosim simulations6. Repair analysis by certain calculation method. 7. Assist on the definition and specification for probecard design.Requirements: 1. Master or PhD degree in Computer Science, Electrical and Electronic Engineering, or relevant.2. Basic knowledge in semiconductor physics, integrated circuits, and IC process technologies.3. Familiar with UNIX or Solaris system 4. Experience in DRAM/NAND Flash test and analysis or DRAM/Flash tester programming (Advantest and Verigy) is desired.5. Solid Programming skills (C, C++, Perl, etc) is highly preferred,6. Familiar with date analysis tool(JMP) or date programmer software(VBA) base on the excel is a plus.7. Interested in working in a lab-environment and conducting hands-on measurements (memory tester, oscilloscope, logic analyzer, etc).8. Highly motivated and engaged, independent problem solving skills, good communication and presentation skills.9. Willing to work under pressure, willing to travel.10. English language skill in writing and speaking is a must.

立即申请
收藏

财务/会计实习生 西安紫光国芯半导体有限公司 西安 70元/天 03-22

学历要求:本科|工作经验:2年|公司性质:国企|公司规模:150-500人

工作职责:1. 负责日常现金及银行业务的办理;2. 税务申报和相关材料的准备工作。3. 负责费用稽核报销;4. 负责固定资产的管理及账务处理;5. 配合部门经理做好各种帐目处理;6. 完成上级领导交付的其他工作。职位要求:1. 本科以上学历,会计、财务相关专业;2. 英语四级以上,具备较强的英语读、说、听、写能力;3. 熟练使用office系列办公软件,熟悉银行、纳税申报等的办理;4. 责任心强,作风严谨,具有较强的人际沟通、组织能力及良好的团队合作精神。

立即申请
收藏

数字后端工程师 西安紫光国芯半导体有限公司 上海-浦东新区 20-35万/年 03-22

学历要求:本科|工作经验:|公司性质:国企|公司规模:150-500人

以下招聘职位均为公司设计服务部门的工程师职位,为上海大型国际IC公司以及国内顶端IC公司提供on-site设计服务。西安紫光国芯的设计服务部门能够提供高端设计服务,具备从设计规格到芯片流片完整流程的设计经验,包括:设计实现、功能验证、综合和DFT、物理实现、时序和物理检查、流片。公司在过去几年中成功为客户完成了十几款SoC在65nm/40nm/28nm/14nm工艺上的SoC芯片设计和流片,帮助客户低成本的、高效的实现产品化,是目前国内最大的设计服务外包服务商,所服务的客户均为国际知名大型芯片设计公司以及国内顶端芯片设计公司,具备一流的技术及设计环境以及良好的文化氛围,我们的员工在客户端承担核心技术板块,使其可以快速稳定成长。 我们各个业务板块均提供先进的设计开发环境,良好的企业文化以及人文关怀,优厚的薪酬待遇,完善的休假体系,全面的社会及商业保险。诚邀有志IC事业的人才加盟共同发展!Responsibilities:1. Responsible for Synthesis, timing closure2. Responsible for developing digital designs with emphasis on backend, including Floor-plan, power planning, Place, CTS and Route. 3. Work with Front-end designers to optimize timing/area/power of the design implementation and perform static timing analysis.4. Optimization and Verification of layout for tape-out (including RC extraction, ECO, DRC, LVS).5. Power IR drop analysis and optimization, area and parasitic layout optimization, chip size optimization.6. Static Timing analysis (Prime Time) and setup/hold fix.7. Formal Verification for equivalence checking (Formality).8. Generation of fill structures according to technology requirements.Requirements:1. 2-4 years experience in backend design flow (APR) with proven SOC tape-out experience.2. RTL(verilog) coding and style checking3. Scripts based on makefile, perl, TCL or csh/tcsh 4. Clock-domain-cross checking 5. Logic synthesis or physical Synthesis(Design Compiler)6. Static timing analysis (Primetime)7. Experienced in Synopsys/Cadence automatically physical implementation tools and flows (IC-Compiler/ Astro / SOC-Encounter/ Milky-way/ Star-RCX) is a plus.8. Experience with one or more scripting languages (Perl, TCL, or Shell) to make reusable automatically flow is a plus.9. Experience and knowledge about FE design (RTL code, flow) and verification is a plus.10. Good analytical and debugging skills.11. Good command of English.Responsibilities:1. Responsible for developing digital designs with emphasis on backend, including Floor-plan, power planning, Place, CTS and Route.2. Work with Front-end designers to optimize timing/area/power of the design implementation and perform static timing analysis.3. Optimization and Verification of layout for tape-out (including RC extraction, ECO, DRC, LVS).4. Power IR drop analysis and optimization, area and parasitic layout optimization, chip size optimization.5. Static Timing analysis (Prime Time) and setup/hold fix.6. Formal Verification for equivalence checking (Formality).7. Generation of fill structures according to technology requirements.Requirements:1. Experienced in Synopsys/Cadence automatically physical implementation tools and flows (IC-Compiler/ Astro / SOC-Encounter/ Milky-way/ Star-RCX) is a plus.3. Experience with one or more scripting languages (Perl, TCL, or Shell) to make reusable automatically flow is a plus.4. Experience and knowledge about FE design (RTL code, flow) and verification is a plus.5. Good analytical and debugging skills.6. Good command of English

立即申请
收藏

设计验证工程师 西安紫光国芯半导体有限公司 上海-浦东新区 20-35万/年 03-22

学历要求:本科|工作经验:|公司性质:国企|公司规模:150-500人

Responsibilities:1. According to the design specification, be responsible for the verification plan and verification objective definition.2. Test-bench development (modeling, assertions, checkers, monitors, score-board, regressions, coverage), test-case development (sequence, VRAD) and integration.3. Work with Random Verification methodology(VMM, OVM, UVM, eRM)4. Work as an independent verification engineers to check the design functionality at SOC module level and chip level.5. Work as interface with Front-End and Back-End engineer to optimize or review the design architecture and implementation.6. Verilog or VHDL coding according to design specification or external/internal IP integration.7. Support the post simulation with gate-level verilog or VHDL net list.Requirements:1. Either Bachelor, Master or PhD in Microelectronics, Electronic Engineering, or related field, 2+ Years of verification working experience.2. Experience with Verification language (SPECMAN/E-language, System-Verilog, Vera)3. Experience with RTL coding and simulators (Modelsim, NC-sim).4. Basic knowledge of script language (Perl, TCL, C-language and so on)5. Knowledge about 2G/3G/LTE handset baseband Architecture, ARM, AHB Architecture is a plus.6. Knowledge about Baseband chip peripheral (USB2.0/USB3.0, SSIC, MIPI) is a plus.7. Team oriented, love to work in young, international and highly motivated teams.8. Good command of English

立即申请
收藏

数字后端设计工程师 西安紫光国芯半导体有限公司 西安 17-25万/年 03-22

学历要求:|工作经验:|公司性质:国企|公司规模:150-500人

Responsibilities:1. Responsible for developing digital designs with emphasis on backend, including Floor-plan, power planning, Place, CTS and Route. 2. Work with Front-end designers to optimize timing/area/power of the design implementation and perform static timing analysis.3. Optimization and Verification of layout for tape-out (including RC extraction, ECO, DRC, LVS).4. Power IR drop analysis and optimization, area and parasitic layout optimization, chip size optimization.5. Static Timing analysis (Prime Time) and setup/hold fix.6. Formal Verification for equivalence checking (Formality).7. Generation of fill structures according to technology requirements.Requirements:1. 2-4 years experience in backend design flow (APR) with proven SOC tape-out experience.2. Experienced in Synopsys/Cadence automatically physical implementation tools and flows (IC-Compiler/ Astro / SOC-Encounter/ Milky-way/ Star-RCX) is a plus.3. Experience with one or more scripting languages (Perl, TCL, or Shell) to make reusable automatically flow is a plus.4. Experience and knowledge about FE design (RTL code, flow) and verification is a plus.5. Good analytical and debugging skills.6. Good command of English.

立即申请
收藏

数字设计工程师 西安紫光国芯半导体有限公司 西安 17-25万/年 03-22

学历要求:本科|工作经验:|公司性质:国企|公司规模:150-500人

Responsibilities:1. Responsible for developing complex digital designs with emphasis on Front-End, including Coding, Simulation, Constrain and Synthesis. 2. Responsible for developing high-speed digital designs with Schematic, including schematic, simulation and timing/power/performance optimization.3. Check the relative block layout implementation.4. Test-bench and Test-pattern generation to full-cover the relative design.Requirements:1. Either Bachelor, Master or PhD in Microelectronics, Electronic Engineering, or related field +2 years experience, Knowledge.2. experience with digital design (verilog /schematic) and simulation (modelsim,NC-sim, Nanosim) is a plus.3. Team oriented, love to work in young, international and highly motivated teams.4. Good communication skills and High grade of flexibility.5. Highly motivated and engaged.6. Experience in Flash/SRAM and DRAM design is preferred.7. English language skill in writing and speaking is a must.email:hr-xian@scsemicon.com

立即申请
收藏

可测性设计工程师 (DFT) 西安紫光国芯半导体有限公司 西安 17-25万/年 03-22

学历要求:本科|工作经验:1年|公司性质:国企|公司规模:150-500人

Responsibilities:1. Participate in SoC level DFT architecture definition.2. Implement DFT strategy for the SoC chips, cooperating with design team3. Implement basic DFT schemes, including scan, boundary scan, MemBIST and LogicBIST. 4. Develop the high coverage and cost effective test patterns.5. Verify all DFT logics and test patterns with simulation and static timing analysis tool.6. Support other teams for DFT related problems.Requirements:1. Either Bachelor or Master degree, 2+ years related experience required.2. Basic knowledge of IC design flow, including coding, simulation, verification, synthesis and STA3. Good understanding of the General DFT methodology such as BIST, SCAN,JTAG and ATPG.4. Knowledge on and familiar with basic Mentor/ Synopsys DFT flow and tools5. Proficient in Verilog/VHDL language6. Be familiar with Shell/TCL/Perl program, or skilled in C program7. Good English communication skills8. Self-motivated and good team player

立即申请
收藏

设计验证工程师 (DFV) 西安紫光国芯半导体有限公司 西安 17-25万/年 03-22

学历要求:本科|工作经验:|公司性质:国企|公司规模:150-500人

Responsibilities:1. According to the design specification, be responsible for the verification plan and verification objective definition.2. Test-bench development(modeling, assertions, checkers, monitors, score-board, regressions, coverage), test-case development (sequence, VRAD) and integration.3. Work with Random Verification methodology(VMM, OVM, UVM, eRM)4. Work as an independent verification engineers to check the design functionality at SOC module level and chip level. 5. Work as interface with Front-End and Back-End engineer to optimize or review the design architecture and implementation.6. Verilog or VHDL coding according to design specification or external/internal IP integration.7. Support the post simulation with gate-level verilog or VHDL netlist. Requirements:1. Either Bachelor, Master or PhD in Microelectronics, Electronic Engineering, or related field, 2+ Years of verification working experience.2. Experience with Verification language (SPECMAN/E-language, System-Verilog, Vera) 3. Experience with RTL coding and simulators (Modelsim, NC-sim).4. Basic knowledge of script language (Perl, TCL, C-language and so on) 5. Knowledge about 2G/3G/LTE handset baseband Architecture, ARM, AHB Architecture is a plus. 6. Knowledge about Baseband chip peripheral(USB2.0/USB3.0, SSIC, MIPI) is a plus. 7. Team oriented, love to work in young, international and highly motivated teams.8. Good command of English email:hr-xian@scsemicon.com

立即申请
收藏

全选
申请职位
  • 上一页
  • 1
  • 下一页
共1页,到第确定

精英竞拍汇-中高端人才求职平台

互联网专场
招聘职位: 后端开发,前端开发,移动端开发,测试,产品/设计/运营
金融专场
招聘职位: 财务审计,合规与风险控制,后台运营,投行,销售
房地产专场
招聘职位: 房地产开发,建筑工程,规划设计,商业,市场营销
汽车专场
招聘职位: 汽车新能源,软件与汽车电子,生产制造,质量管理,供应链管理