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Layout Engineer美光半导体(上海)有限责任公司上海02-24

学历要求:|工作经验:无需经验|公司性质:外资(欧美)|公司规模:500-1000人

Description: As an IC Layout Design Engineer at Micron's Shanghai Design Center, you will work in a highly innovative and motivated design team using state of the art memory technologies to advance DRAM Memory design. As part of a multi-disciplinary team, you will contribute to physical layout floor plan of various memory chip circuit blocks, and perform block level layout, LVS/DRC verification and using other CAD tools to check layout.Career Path/Development:Global Opportunity:Work closely with Micron's various design/PI/CAD teams in US and other countries to deliver memory products.Provide overseas working opportunity. Acquiring global experience for your future career path within MicronSkill Advancement:Wide exposure to advanced technologies and process nodesLeveraging various resources and tools, like digital place & route and perform verification (LVS/DRC/EM/Totem etc) layout to a FULL-CHIP level supporting project tape outProvide systematic layout training programs for further developmentRequirement: -College degree (or above) in Electrical Engineering or other related engineering field. -Proficiency with Cadence OA and Calibre verification tools desirable. -Understanding of basic CMOS circuits is a plus. -Understanding of DRAM/Flash architecture or previous memory layout experience is a plus. -English language skill in writing and speaking is a plus. -No fresh graduates will be considered. Education: College degree (or above) in Electrical Engineering or other related engineering field.We recruit, hire, train, promote, discipline and provide other conditions of employment without regard to a person's race, color, religion, sex, age, national origin, disability, sexual orientation, gender identity and expression, pregnancy, veteran’s status, or other classifications protected under law. This includes providing reasonable accommodation for team members' disabilities or religious beliefs and practices.Each manager, supervisor and team member is responsible for carrying out this policy. The EEO Administrator in Human Resources is responsible for administration of this policy. The administrator will monitor compliance and is available to answer any questions on EEO matters.To request assistance with the application process, please contact Micron’s Human Resources Department .职位要求:详见职位描述

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结构设计师(000347)(重庆)四川长虹器件科技有限公司重庆02-24

学历要求:本科|工作经验:|公司性质:国企|公司规模:

根据公司经营战略及技术方向,负责新产品开发,为各环节提供技术支持,协同量产产品过程问题分析,并对量产品进行持续的设计优化,积极参与持续改进及其他相关工作。

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ASIC设计后端布局布线工程师创意电子(南京)有限公司异地招聘02-24

学历要求:本科|工作经验:2年|公司性质:外资(非欧美)|公司规模:50-150人

1.执行Netlist-to-GDS设计流程(包含floorplanning, placement, timing optimization, clock tree synthesis and routing.) 2.支援STA时序分析and fixing. 3.实体验证(包含DRC, LVS, IR drop and DFM analysis.)岗位要求:1.BSEE/ME/CE, MSEE/ME/CE is preferred (电子工程/微电子/通讯工程) 2.Interest in IC design implementation 3.Hand-on experience in Synopsys (ICC/ICC2/PT/StarRC) and Cadence (EDI/EPS) is preferred 4.User of Perl or TCL is preferred   工作地点:南京  福利待遇:  1.依您资历核叙薪  2.提供五险一金+团体险,公积金缴纳比例10%  3.入职即享有年休假与带薪病假  4.符合条件者提供宿舍(外地人员优先,由公司统一安排)  5.做五休二  工作地址:     南京市浦口区研创园团结路99号孵鹰大厦C座1401室      

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Physical/Backend Design Engineer超威半导体(中国)有限公司北京02-24

学历要求:本科|工作经验:5-7年|公司性质:外资(欧美)|公司规模:1000-5000人

Role & Responsibilities:Work with global Front-End design team and physical design team for large scale ASIC chip physical implementation. Focus on physical design of deep sub-micron GPU chips including block level (full chip) floor planning, timing closure, place & route, physical verification etc. The individual is expected to be an expert in multiple aspects in PD areas and provide technically leadership to the engineering team. The individual is also expected to be accountable for project delivery.Job Requirements:1. MSEE with 3+ years or Bachelor with 5+ years of industrial experience in ASIC design2. 3+ years or more years of experience in physical design of deep submicron digital ASIC chips3. Hands on experience in large scale ASIC chip physical design4. Knowledgeable in all aspects of deep submicron ASIC design flow5. Successfully gone through several complete product development cycles6. Demonstrate strong leadership and work well with cross-functional teams7. Good listening, writing and speaking English8. Good communication skills, strong interpersonal skills and the flexibility9. Dedicated, hardworking and good team player10. Familiar with Back-End (physical design) EDA tools11. Familiar with Front-End EDA tools is a plus12. Familiar with Unix/Linux environment and good at scriptsWhat you do at AMD changes everything At AMD, we push the boundaries of what is possible. We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center.   Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results. It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world. If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.

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资深IC版图(layout)设计工程师聚辰半导体股份有限公司上海02-23

学历要求:本科|工作经验:5-7年|公司性质:合资|公司规模:50-150人

Key responsibilities岗位职责:?Do IC layout design and simulation参与IC 版图设计与仿真,根据版图工程师的要求完成工作?Work with circuit design engineers to solve potential issues such as ESD, Latch-up, timing, noise and so on.协助电路设计工程师发现和解决设计过程中潜在的问题,如ESD、Latch up、时效、噪音等?Layout verification including LVS, DRC, ERC配合验证、修订等Qualification岗位要求:?BS or higher in Science and/or Engineering areas 微电子、电子工程等相关专业?Be familiar with CADENCE Layout tools of CMOS IC layout.熟悉基于CMOS工艺的CADENCE设计工具?Understand IC design process了解IC设计开发流程?Minimum 5 years IC layout experience 5年以上版图设计经验

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Device Layout Engineer/版图设计工程师昂宝电子(上海)有限公司上海-浦东新区02-23

学历要求:大专|工作经验:2年|公司性质:外资(非欧美)|公司规模:150-500人

工作职责:1、负责半导体器件的版图设计、版图验证,和 Tape out 相关工作2、与设计工程师充分沟通,理解所设计器件的平面和纵向结构,确保完全理解器件设计对版图的要求;3、相关文档的撰写;4、具有半导体器件、工艺经验者优先。任职资格:1、微电子、电子工程专业本科以上学历,版图经验丰富者可放宽至大专;2、二年以上layout经验,有半导体器件、工艺经验者优先;3、能熟练使用主流版图设计工具,如Virtuoso、Laker、Ledit等;4、熟悉版图设计方法和技巧,能高质量独立完成版图设计,和产品Tape Out相关工作;5、熟悉半导体器件工艺流程、集成电路CMOS工艺流程,以及半导体器件基础知识;6、工作态度积极主动,具有良好的沟通能力和团队合作精神,以及良好的英语读写能力。

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PCB layout工程师艾德克斯电子(南京)有限公司南京-雨花台区02-22

学历要求:大专|工作经验:2年|公司性质:外资(非欧美)|公司规模:150-500人

岗位职责:1. 协助RD、结构完成符合工艺、功能的PCB设计,并制作gerber文件,回复板厂工程问客;2. 熟悉数字电路、模拟电路和开关电源电路,对ESD、EMC、安规有一定的认识;3. 熟练操作Altium Designer 软件或相关软件,具有四层板、阻抗匹配设计经验优先;4. PCB和原理图封装制作和维护;5. 熟悉PCB生产制作和贴片、DIP、组装工艺,协助生产制定PCB改善方案并进行维护。岗位要求:1. 电子、电气相关专业毕业,专科及以上学历;2. 有多层板经验者优先;3. 对DFM/DFT有一定的基础;4. 有很强的责任心,做事认真谨慎注重细节,善于发现创新; 5. 有良好的工作规划能力、沟通能力、协调能力、学习能力。此岗位将提供具有市场竞争力的薪资区间。

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版图设计工程师Layout engineer台积电(中国)有限公司上海02-22

学历要求:本科|工作经验:|公司性质:外资(非欧美)|公司规模:1000-5000人

What we do 负责先进制程及工艺的layout设计/IO全布局设计/SRAM。 负责物理验证(DRC/LVS/Antenna)。 负责测试芯片版图设计及验证。 负责与设计人员密切合作,优化产品性能功耗面积。                    Who we look for 熟悉版图设计和验证工具(Virtuoso,Laker,Calibre)。 熟悉先进工艺的设计原则和布局效果。 优秀的沟通技巧和团队合作精神。 具有编程经验(Perl/tcl技能)和N16相关经验者优先。                    欢迎具有微电子、物理等相关领域知识的本科含以上优秀应征者加入我们。

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NO.2004 IC版图设计工程师(2020应届生)珠海全志科技股份有限公司西安-高新技术产业开发区02-21

学历要求:|工作经验:|公司性质:民营公司|公司规模:500-1000人

一、 任职资格1、本科、硕士学历,电子微电子、集成电路系统、电子科学、电子通信或物理等相关专业;2、了解半导体器件物理、CMOS集成电路制造工艺,集成电路设计(数字、模拟);3、 掌握主流EDA工具的使用。二、职位描述负责完成模拟、数模混合、射频电路的版图设计、版图验证以及芯片物理验证工作。三、职位方向模拟后端及芯片顶层整合。

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模拟/射频layout版图设计工程师翱捷科技(上海)有限公司上海-浦东新区02-21

学历要求:本科|工作经验:|公司性质:合资|公司规模:500-1000人

职责描述:1)与射频模拟电路设计工程师一起完成器件摆放和版图floor-plan2)根据确定好的Floor-plan完成版图设计和验证工作包括 LVS DRC ERC等3)协助射频模拟电路设计工程师对关键电路的版图进行后仿参数提取和版图优化应聘要求:1)熟悉Linux/Unix 系统基本操作2)了解基本射频模拟电路结构和工作原理3)熟悉深亚微米CMOS工艺版图设计规则,如55nm/40nm/28nm/16nm4)熟练使用版图设计EDA工具如Virtusuo, Calibre, etc等进行版图设计和参数提取5) 喜欢版图设计,能与电路设计工程师进行良好的沟通,工作年限没有特别要求6)具备良好英语读写能力,准确理解pdk等英文文档

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模拟IC版图设计工程师上海艾为电子技术股份有限公司苏州02-21

学历要求:本科|工作经验:3-4年|公司性质:上市公司|公司规模:150-500人

岗位职责:根据电路原理图进行模拟及混合信号电路版图设计与电路设计工程师合作,优化版图确保电路性能最优化完成版图物理验证完成Sign-off流程及检查,编写版图设计文档 任职要求:电子类相关专业,本科或本科以上学历3年以上版图设计工作经验,有实际tape out经验者优先熟悉ESD、Latch Up原理及相应的版图预防对策具有良好的学习能力、沟通协调能力和团队合作精神

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IC版图设计工程师/IC Layout Engineer广州昂宝电子有限公司广州-黄埔区02-20

学历要求:本科|工作经验:2年|公司性质:外资(非欧美)|公司规模:150-500人

  Job Description:  -This full time position involves the design of integrated circuits and cells using IC design CAD tools.   -The applicant should be familiar with polygon editors, extractors, and layout verification software.   - Any experience with Cadence virtuoso suite layout tools would be considered as a plus. 职位描述:1.       负责模拟集成电路的版图设计和版图验证;2.       与设计工程师充分沟通,确保完全理解设计对版图的要求;3.       熟练使用主流IC版图设计和验证工具,有Cadence Virtuoso suite工具经验优先。    Requirements:  - An associate degree in electronics or the equivalent  - 2 years of prior experience as a layout engineer   - Good communication skills and team player  职位要求:1.       微电子、电子工程相关学历;2.       两年以上IC layout经验,有先进工艺模拟版图经验者优先;3.       具有良好的沟通能力和团队合作精神。

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存储器版图设计工程师华润上华科技上海-静安区02-20

学历要求:本科|工作经验:3-4年|公司性质:国企|公司规模:1000-5000人

1.了解存储器的版图设计方法;2.能够清晰理解并执行前端对后端得设计需求;3.熟练使用calibre进行版图验证;4.能够完成后续版图gds的tape out所有文档的填写和备份;5.能够完成版图数据备份和维护。   任职资格:1.微电子或者理工科相关专业,本科及以上学历;2.熟悉常用的EDA和办公软件;3.2年以上模拟版图后端设计经验;4.容易沟通,工作认真负责,有热情;5.具有Memory版图设计经验优先考虑。    工作地点:无锡/上海

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集成电路版图设计工程师上海东软载波微电子有限公司苏州-工业园区02-20

学历要求:本科|工作经验:5-7年|公司性质:民营公司|公司规模:150-500人

主要职责:1、负责模拟和射频等定制IP模块的版图设计实现;2、与模拟前端设计工程师密切合作,确保版图设计质量;3、独立完成版图数据的验证工作,熟悉design rule,并能进行修改完善;4、针对不同生产工艺,不同IP模块,编写完善版图设计流程规范。相关技能素质要求:1、熟悉半导体制造工艺流程,掌握电路基础知识;2、熟练使用版图设计的常用EDA工具;3、独立完成DRC和LVS过程,并进行问题分析解决;4、独立绘制模拟和射频IP模块,熟悉I/O pad,Standard Cell,ADC等版图实现;5、具有以下经验优先:能使用P&R工具,有40nm等工艺版图设计经验;6、优秀的职业素养,良好的沟通和协调能力,良好的团队意识和合作精神。工作经历要求:5年以上模拟和射频模块版图设计工作经验。

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Layout Engineer 模拟版图工程师豪威科技(上海)有限公司上海-浦东新区02-20

学历要求:本科|工作经验:5-7年|公司性质:外资(欧美)|公司规模:1000-5000人

Position Overview:Responsible for IC full-custom analog layout, verification of the layout (DRC/ERC/LVS), RC extraction for post simulationResponsibilities:Primary (70%):1.Full custome analog layout/verification and RC extraction.2.Perform block level layout. Conduct physical verification (DRC and LVS using Cadence tools).Secondary (30%):1.Team work with analog designers, optimize layout.2.Perform floor planning and placements (pad locations and custom routing).Requirements:1.Bachelor or above degree with 5 years experiences in CMOS IC full-custom layout.2.Experiences in Mixed signal/analog/high speed layout.3.Familliar with layout skills and knowledge is must.4.Good teamwork/communication/positive is must.5.Familiar with Cadence IC layout and verification tools6.Having massive IP block experiencePlus:1.Familiar with 0.18/0.13/0.09/0.065/0.04 um CMOS process and design rule is a plus.2.Familiar with ESD/Latch up/antenna and related layout solutions is a plus.3.Familiar with layout size reduction is a plus, with standard cell experience is good.4.Familiar with rule deck is a plus.

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Analog IC Layout Design Engineer德州仪器半导体技术(上海)有限公司上海-浦东新区02-20

学历要求:本科|工作经验:5-7年|公司性质:外资(欧美)|公司规模:150-500人

Texas Instruments Incorporated (TI) is a global semiconductor design and manufacturing company that develops analog ICs and embedded processors.In this role your primary activities will Include: Floor-plan, layout, and verification of complex circuits. Optimize layouts with conflicting specifications. Shield signal lines from clock lines. Determine most efficient routing technique to minimize vias in the signal paths Guard ringing. Efficient techniques for matching, low-offset, and performance. Other, related activities Include: Responsible for design rule and schematic verification, manufacturability, verification, bonding, stepper utilization, electromigration and ESD verification. Ensure that all layout design operations meet design, mask,, and fab requirements. May also require analog layout experience and proficiency with high-voltage analog layout and device matching. Basic Qualifications: Bachelors Degree, or equivalent 5+ years of related experience Strong schematic-to-layout translation skills width Layout-XL Preferred Qualifications: Analog layout experience and proficiency with high-power analog layout and device matching. Layout of power devices. Familiarity with the following tools: Cadence schematic capture and layout tools; Cadence/Mentor/Synopsys LVS/DRC verification tools.

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Analog Layout Engineer 版图设计工程师Cadence(上海楷登电子科技有限公司)上海-浦东新区02-19

学历要求:|工作经验:|公司性质:外资(欧美)|公司规模:500-1000人

Job DescriptionPosition Description: ?Skillful capable of AMS layout Design area: Matching sense from transistor, Resistor and capacitor, Power and Ground coupling, Signal path from Differential pairs, etc.?Proficient with Cadence layout tools specifically Virtuoso XL and Assura (Cadence 6.1 experience a plus) ?Ability to coordinate with the other analog IC circuit layout, ensuring robust, efficient, consistent and successful delivery of analog IC circuit layout.?Fundamental understanding of IC design technology and process/methodology?Skilled in Analog IC top level chip assembly including floorplanning and block layout?Hands-on experience conducting DRC/LVS analysis and recommending appropriate solutionsPosition Requirements:BSEE degree with 2+ years of applicable experience in analog design industry.Essential that the individual demonstrates strong communication, verbal and written, and project management skills.Requires good communication skills in English and Chinese.

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模拟版图设计工程师(MCU方向)0819北京兆易创新科技股份有限公司异地招聘02-04

学历要求:|工作经验:1年|公司性质:上市公司|公司规模:500-1000人

岗位职责:负责模拟版图设计工作。 任职资格:1.微电子、电子工程相关专业,本科以上学历; 2.熟悉模拟版图设计,有一定的模拟电路基础; 3.熟悉virtuoso,熟练使用calibre进行DRC、LVS检查; 4.有PLL/ADC/DAC/BGR等模拟模块版图设计经验优先考虑; 5.熟悉SKILL/perl/TCL等编程语言优先考虑; 6.有大型芯片模块整合工作经验优先考虑; 7.有65nm以下工艺经验优先考虑; 8.诚信正直,踏实努力,具有较强的抗压能力; 9.具有良好的沟通能力、学习能力、分析能力和团队合作能力。

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IC Layout design engineer/IC版图工程师_AE博世(中国)投资有限公司上海01-28

学历要求:|工作经验:5-7年|公司性质:外资(欧美)|公司规模:10000人以上

Company DescriptionDo you want beneficial technologies being shaped by your ideas? Whether in the areas of mobility solutions, consumer goods, industrial technology or energy and building technology - with us, you will have the chance to improve quality of life all across the globe. Welcome to Bosch.Job DescriptionResponsible for IC full-custom analog/mix-signalCHIP/IP layoutVerification of the layout (DRC/ERC/LVS)RC extraction for post simulationAssist in project tapeout.Cooperate with design team in Germany QualificationsBSEE with 2+ years of CMOS analog/mix-signallayout experienceFamiliar with Cadence and Calibre/Assura layoutand verification toolsUnderstanding of basic CMOS circuits is a mustUnderstanding of CMOS process is a mustWork experience in an international teamDedicated, hardworking and good team playerEnglish language skill in writing and speakingis a mustAdditional InformationInternal referral bonus of this vacancy: RMB3000(Valid only for Bosch associates);

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PCB layout engineer/PCB布线工程师_AE博世汽车部件(苏州)有限公司苏州01-28

学历要求:|工作经验:3-4年|公司性质:外资(欧美)|公司规模:5000-10000人

Company DescriptionDo you want beneficial technologies being shaped by your ideas? Whether in the areas of mobility solutions, consumer goods, industrial technology or energy and building technology - with us, you will have the chance to improve quality of life all across the globe. Welcome to Bosch.Job DescriptionJob Responsibilities/工作职责:PCB Layout for electronic control units of automotive and non-automotive products负责汽车/非汽车类产品电子控制单元的PCB布线设计PCB layout to fulfil mechanical, HW, EMC and production process technical requirementPCB布线设计满足机械、硬件、EMC和生产工艺技术要求Organizing layout review together with hardware, mechanical, EMC and manufacture engineer to ensure layout quality组织硬件、机械、EMC和生产工程师进行Layout检查来确保Layout质量Responsible layout concept study for new products负责新产品的layout概念设计Estimation of efforts and schedules for layout projects规划Layout项目的时间和成本Close cooperation with international development teams与国际化团队的密切合作QualificationsBachelor or above in Electronics engineering电子工程类本科及以上学历3-5 years PCB layout design experience or HW design experience for automotive or Non-automotive products3-5年PCB布线设计或硬件设计工作经验(汽车或者非汽车类产品)Knowledge of digital, analog circuits and EMC熟悉数字电路,模拟电路和EMC的相关知识Experience of Circuit design, Layout tool(ZUKEN/Allegro/PADS/Altium/etc. , ZUKEN is preferred)具有以下工作经验:电路设计,Layout工具(ZUKEN/Allegro/PADS/Altium/etc. , ZUKEN优先)Self-motivated, excellent communication skills and team spirit积极主动,优秀的沟通能力和团队合作精神Good English communication skill英语听说读写流利Willingness to work and interact in international teams积极融入并在国际化团队中发挥作用Additional Information该岗位内部推荐奖金为人民币3,000元整(仅限博世内部员工申请),具体请参见《博世中国内部推荐政策》? Internal Referral bonus of this vacancy: RMB 3,000 (Valid only for Bosch associates). For the detailed regulation, please refer to Bosch China Internal Referral Policy

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